Comparison of different design techniques of XOR & AND gate using EDA simulation tool

XOR & AND gates are most important basic building blocks of any VLSI applications. These gates can be implemented in different architectures by using different circuit designs techniques. This paper evaluates and compares the performance of various design techniques of XOR-AND gates. The performances of these techniques have been evaluated by Tanner Tools V13 using the 90nm CMOS technology. In this work, XOR & AND gates can be implemented using seven different logic design techniques i.e. Standard CMOS logic, PTL logic, CPL logic, DPL logic, DVL logic, GDI logic and Domino logic. The XOR gates with PTL design are suitable for arithmetic gates and other VLSI applications with very low power consumption and a very high speed performance and the AND gate GDI design has better performance than other design techniques.